Beginning Logic Design
The Beginning Logic Design is a work in progress series that covers topics to become familiar with logic design. It begins with small designs with logic gates and progresses to cover various topics on using SystemVerilog and Vivado.
- Part 1 – Logic Gates
- Part 2 – 4 Bit Adder
- Part 3 – Latches and Flip Flops
- Part 4 – Hello SystemVerilog
- Part 5 – ALU Design 1
- Part 6 – ALU Design 2
- Part 7 – ALU Design 3
- Part 8 – Bidirectional Bus, RAM and ROM
- Part 9 – State Machine to Build a Batch Adder
- Part 10 – CPU Outline and Foundation
- Part 11 – CPU LOAD and STORE
- Part 12 – CPU Branching Operations
- Part 13 – CPU ALU Instructions
- Part 14 – CPU Stack and Subroutines
Hello AFU
The Hello AFU series steps through building a basic CAPI design.
- Part 1 – Base Setup and Simulation
- Part 2 – Driving and Shifting Signals
- Part 3 – MMIO Handling
- Part 4 – Application Interface
- Part 5 – State Machine and Reading
- Part 6 – Parity and Writing
- Hello AFU on Alpha-Data KU3
