Hello and welcome to part 4 of my Beginning Logic Design series.
In the last couple posts we used Logicly to cover some introductory topics such as the basic logic gates, some combinational circuits for doing addition, and some sequential circuits we can use to store bits of data.
As we move on I’d like to cover increasingly more useful building blocks, but we’ll quickly outgrow what we can manage nicely in an educational logic simulator. While you can persevere and eventually build an entire CPU in Logicly, this is difficult and impractical.
Another reason to move beyond the basic logic simulator is I’d like to build some of these designs to see them operate in real life. While I have admiration for the folks that are building computers from scratch, I’d like an easier way. So today we’re going to change things up significantly!
Today we’re going to start exploring SystemVerilog and FPGAs!
System What Now?
SystemVerilog is a hardware description language (HDL). An HDL is a language that lets you describe hardware with code, rather than designing with schematics.
This gives a ton of benefits. Primarily it let’s us focus more on what we’re trying to accomplish, rather than some of the nifty tricks we have to do with basic logic gates to implement designs. We give our HDL to programs that can convert our descriptions into actual designs.
SystemVerilog and similar languages play a large role in the design of modern integrated circuits. This is especially true in the design of ASICs and designs for FPGAs. Since building your own ASIC has a fairly high cost for a hobbyist, we’ll look at FPGAs and tools provided by the vendors that make them.
Getting Started With FPGAs
There are two massive FPGA focused companies and a few other notable contenders. The biggest players are Altera (now owned by Intel) and Xilinx. Since the two big guys each have roughly 1/3 of the FPGA market it’s best to start with one of them since it’s easier to find boards and documentation.
I am more familiar with the Xilinx tools and I find their software, Vivado, is a bit less cluttered and makes simulation a bit easier, so I’ll be using that.
To get started you’ll need to register a free Xilinx account and download Vivado. The download is several gigabytes so it will take some time to download and install.
Hello Vivado
Using these tools can be daunting, so let’s jump right in and get something basic going before we get cold feet. Let’s open Vivado!
We’ll hit Create Project and step through the wizard. The first page of the wizard will introduce itself, then we’ll be prompted to name the project and select a directory for it to live in. I’ll call mine hello-vivado and store it in /tmp since I don’t intend to keep this project.
On the next page, I’ll select the project type, I’ll choose to RTL Project so we are ready for anything. I’ll skip the option to specify sources at this time.
The next page confused me a lot when I first tried to use Vivado with minimal FPGA experience, it asks you to pick a default FPGA out of their catalog of a bajillion parts. For simulated projects it doesn’t really matter, but I intend to buy the Arty A7 development board in the near future so I can run my designs on real hardware. I’ll choose the Artix-7 FPGA that board uses, part number xc7a35ticsg324-1l.
With that selected we can hit next and finish to get into our project.
There is a ton of functionality in Vivado, but we’ll ignore a lot of it for now. Let’s add a new file to our Sources. There is a plus sign we can use to add a new source file.
In the prompt that comes up, select Add or create design sources, and hit next. The screen will now present an interface for you to add or create files.
I’ll click Create File and select SystemVerilog as the file type. A common practice in FPGA design is to encapsulate your whole design as a module named top, and I will follow that convention.
I’ll hit OK followed by finish to close out of the add/create dialog. After you hit finish another prompt will come up to help you name the module and add I/O ports (similar to the connections that we had on components made in Logicly.) Just hit OK to accept its defaults and OK again to confirm. We’ll now have our top module in the Design Sources of our project.
We can double click on the top.sv file to open it in an editor. Vivado creates SystemVerilog files with a large comment for documenting some notes about the module, for brevity I’ll be deleting those comments from my files and I’ll indent things a bit differently.
- `timescale 1ns / 1ps
- module top ();
- endmodule
This is our new empty module! The `timescale at the top tells the hardware simulator that we want to look at time measured in nanoseconds (a billionth of a second) and have values rounded to the nearest picosecond (a trillionth of a second).
The module keyword starts our description of a module named top. The parenthesis between top and ; is where we can describe the signals coming in and out of our module. The endmodule keyword indicates the end of our module definition.
To start, let’s recreate our 1 bit half adder from the second post. That component took 2 inputs, a and b and returned a sum and a carry. The first step is to add our inputs and outputs to the module.
- module top (
- input logic a,
- input logic b,
- output logic sum,
- output logic carry
- );
SystemVerilog has logic operators that are syntactically similar to most C-influenced languages.
We can use the assign keyword along with our logic operators to implement our half adder. This assignment goes within our module definition.
- `timescale 1ns / 1ps
- module top (
- input logic a,
- input logic b,
- output logic sum,
- output logic carry
- );
- assign sum = a ^ b,
- carry = a & b;
- endmodule
Our half adder is done, let’s see it in action! We can start a simulation by looking for Run Simulation in the Flow Navigator on the left or from the Flow menu in the menu bar. We’ll select Run Behavioral Simulation since we’re not worried about timings for this design.
When we start the simulator, Vivado will elaborate the design, this means interpreting our HDL and determining how that design can be built. It’ll then open a new interface to let us interact with the simulated design.
The leftmost panel shows us the various modules in our design. The middle panel shows us the objects that are part of our selected module. The panel on the right opens up a wave viewer so we can watch the specific signals we’re interested in. Right now it shows our modules inputs and outputs.
It ran our simulation for some time too, a million picoseconds (1000 nanoseconds) have flown right by! We can use the zoom controls in the wave viewer to see everything that’s happened. So far, we haven’t set inputs to any value so the outputs are currently undefined.
To set a to a value, somewhat like we did with the toggle switches in Logicly, we can right click on a from the Objects panel or from the waveform viewer and choose Force Constant...
I’ll set a to 1 and b to 0 using this method. Then to continue simulation, we can use these time controls that are near the top of Vivado.
The play button will run the simulation indefinitely, which is not helpful in this case. I’ll instead edit the runtime field to run for 1 us (microsecond), and click the play with (T) to simulate for that specific amount of time.
After running one more microsecond, you can see the sum and carry did respond appropriately to our input on a and b. I can continue to change the values to validate the modules operation, but will leave it there for now.
Now we know that this design works, let’s look at it! In the Flow Navigator under RTL ANALYSIS we can click on Open Elaborated Design and look at the schematic that was built from the HDL.
Well doesn’t that look familiar! That will conclude this post of my Beginning Logic Design series, as always please leave any questions or feedback you may have in the comments! Keep tinkering!
