Beginning Logic Design – Part 3

Hello and welcome to Part 3 of my Beginning Logic Design tutorial series!

In the last post we explored a common combinational circuit, the adder. In this post I’ll explore some of the basic sequential logic elements: latches and flip-flops.

Sequential Circuits

So far, the circuits I’ve shared are pretty linear. The schematic diagrams have had inputs on the left and all signals move toward the outputs on the right. For sequential circuits, there is an element of feedback where some outputs are routed back into an earlier gate.

Let’s look at the concept of feedback using the NOR gate as our base. I’ll provide one switch as input, and I’ll use it’s own output as the second input.

NOR gate with feedback

In this configuration, the NOR cannot yet determine what it’s output should be, let’s look at the truth table for NOR to understand why.

NOR truth table

Looking at the truth table, if we only know one of the inputs and we know that it’s 0, we can’t determine the output. On the other hand if we know one of the inputs is 1 we can safely say the output is 0.

Now the second input is also known, but something interesting happens if we turn the switch off now.

A confused NOR gate

When the switch is off, the NOR gate will flip its output back and forth due to the feedback loop. When the gate sees the 1 on its 2nd input it changes its output to 0, when it then sees both inputs as 0 it again starts to output 1. If we turn the switch back on, it again doesn’t matter what the second input is set to, the output will be locked to 0.



The Set-Reset Latch

The sequential circuit with the single NOR doesn’t give us a very useful function. It initially has an undefined output state after which it can either have an off state when we give it an input of 1 or a crazy flipping back and forth state when we input 0. A design called the SR (Set-Reset) latch can provide a more useful operation. It is like the previous design but with two sides and the NOR gates providing feedback to each other.

The Set-Reset latch

Just like before, the initial output cannot be determined. This time, by turning the top switch on, the top NOR will now have a known output of 0. This will also cause the bottom NOR to have a known output  of 1 because both of its inputs are now 0. Since the bottom output is now 1, the top NOR will stay 0 as the top switch goes back off.

Setting the SR latch

When both inputs are 1, both outputs are 0 since neither NOR gate has the two 0 inputs needed to output 1.

SR latch with both inputs high

The first switch to toggle to 1 will have its NOR gate toggle output to 1 which will lock the opposite NOR gate to 0.

Looking at the overall behavior of the SR latch

By convention, we refer to one of these inputs as set and the other as reset.The output state of a latch is usually labeled as Q and sometimes the latch will also output the opposite of Q. In this design Q is the output from the NOR gate on the reset side of the design. Since the design is symmetrical, it doesn’t matter which side you choose to be set or reset.

SR latch with labels

Here’s a table that describes the various interactions we see for this design.

SR latch operations table

Since !Q is expected to be the opposite of Q, the outputs are not considered valid with both inputs are 1 as that results in both outputs being 0.  There is another model for the SR latch that is built using an AND, OR and NOT gate to prioritize reset over set.

SR and-or implementation

In this design there is no !Q output and if reset is 1, the value of set is effectively ignored since the AND gate here will never output 0 when reset is 1.

There is also a way to make a similar SR latch with NAND gates, though it has inverted operations where the output is stable when both inputs are 1 and you drop an input to 0 to set or reset the output.

NAND based SR latch in reset state

The last variation of the SR latch I want to share is the gated SR latch, which adds an enable input that assist in controlling the latch operation.

SR latch with enable input

The addition of the AND gates with enable input give you a bit extra control of when state changes are allowed. When the enable input is 0, it will preserve the latches state. This allows you to setup set and reset as you’d like, when you’re ready for the latch to operate you can toggle enable on and off to perform the operation.

Using enable to control when the SR latch changes state

The SR latch is quite common and useful, and can be used as a basis for other common latches.

The Gated D Latch

I am a fan of the gated D latch, it is a slight variation to the SR latch that gives you a simple way of storing a single bit of information. By renaming set to data, and replacing reset with the inverse value of data, we provide our bit to store via the data input and use enable to control when that data is latched.

A D latch design

This design removes the possibility of an input state that would set both Q and !Q to 0, and lets use use a single input to choose if Q will be 1 or 0.

D latch in action

When Latches Become Flip-Flops

In the components section of Logicly there are a few objects under the category Flip-Flops. There are SR, D, JK and T flip-flops. Latches and flip-flops are commonly confused. The first few designs we looked at have no inputs intended for synchronization, these are just called latches. We then looked at gated latches, which add an enable input so that we can control when the data on the other input lines should be treated as valid. With a gated latch, the entire time the enable signal is active, changes to the other inputs will affect the state of the latch. The special bit about a flip-flop is that the state of the latch is limited to the transition of enable from low-to-high (rising or positive edge) or high-to-low (falling or negative edge).

Diagram showing some features of a clock signal

A gated latch can be affected by it’s input during one half of the clock period, while a flip-flop is at a point in time. This is very helpful for digital designs that need more precise timings, such as a CPU.

The easiest way to build my own D flip-flop would be to first save my gated D latch as a component.

Creating a D latch IC

Now, I’ll place two D latches in my design and route the q output of the first to the data input of the second. By connecting a clock to the enable input of the first, and providing the inverted clock signal to the second, it creates a circuit that will only change the output on the falling edge of the clock signal.

Falling edge triggered D flip-flop

Now that’s a functional flip-flop! I encourage you to build this design yourself and play with the input as the clock changes to watch how it will only change as the clock transitions from 1 to 0.

To make a flip flop that triggers on the rising clock edge, route the inverse clock to the first latch, and the normal clock to the second latch.

Rising edge triggered Flip Flop

With that we now know how we can build our very own flip flops to store individual bits of data! For continued exploration on latches and flip flops, I encourage you to dive into the web and build your own JK and T type flip flops. You may also notice that the D flip-flops in logicly have some extra inputs for clear and preset; you can explore what those asynchronous inputs provide and see if you can add that functionality to your own flip flop implementation! It will all sink in with practice!

That wraps it up for this post. If you have any questions or feedback I would love to see your submission in the comments. Keep tinkering!

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